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Datasheet File OCR Text:

TDA7719
3 band car audio processor
Features
Input multiplexer - Multiple input configuration for different application Loudness - 2nd order frequency response - Programmable center frequency - 15dB with 1dB steps - Selectable high frequency boost - Selectable flat-mode Volume - +15dB to -15dB with 1dB step resolution - Soft-step control with programmable blend times Bass - 2nd order frequency response - Center frequency programmable in 4 steps - Q programmable 1.0/1.25/1.5/2.0 - DC gain programmable - -15 to 15dB range with 1dB resolution Middle - 2nd order frequency response - Center frequency programmable in 4 steps - Q programmable 0.5/0.75/1.0/1.25 - -15 to 15dB range with 1dB resolution Treble - 2nd order frequency response - Center frequency programmable in 4 steps - -15 to 15dB range with 1dB resolution Speaker - 4 independent soft step speaker controls - 0dB to -79dB with 1dB steps - Direct mute Subwoofer - 2nd order low pass filter with programmable cut off frequency - 2 independent soft step level control,
TSSOP28
Mute functions - Direct mute - Digitally controlled SoftMute with 4 programmable mute-times Offset detection - Offset voltage detection circuit for on-board power amplifier failure diagnosis Level meter - Provide rectified level voltage of main source signal (before loudness) Rear seat selector - Full source selector for rear seat output Mixing selector

Description
The TDA7719 is a high performance signal processor specifically designed for car radio applications. The device includes a high performance audioprocessor with fully integrated audio filters and new Soft Step architecture. The digital control allows programming in a wide range of filter characteristics. By the use of BCMOSprocess and liner signal processing low distortion and low noise are obtained. Table 1. Device summary
Package TSSOP28 TSSOP28 Packing Tube Tape and reel
Order code TDA7719 TDA7719TR
January 2008
Rev 2
1/45
www.st.com 1
Contents
TDA7719
Contents
1 2 Block circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical specifications and characteristics . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 4.3 Input stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.1 4.3.2 4.3.3 4.3.4 Loudness attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Peak frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High frequency boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Flat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 4.5 4.6
SoftMute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SoftStep volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6.1 4.6.2 4.6.3 4.6.4 Bass attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.7
Middle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.7.1 4.7.2 4.7.3 Middle attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Middle center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Middle quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8
Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8.1 4.8.2 Treble attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Treble center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/45
TDA7719
Contents
4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16
Subwoofer Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Softstep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC offset detector and level meter option . . . . . . . . . . . . . . . . . . . . . . . . 25 DC offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Level meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Audioprocessor testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Test circuit (3 x QD + 1 x FD + DC offset detector) . . . . . . . . . . . . . . . . . 27
5
I2C Bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1.1 5.1.2 5.1.3 Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2
Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6 7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3/45
List of tables
TDA7719
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Selector configuration matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Available sources for mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input configuration / main selector (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2nd Source selector / direct path (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Mixing source / mixing gain (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Mix control / level meter / dc offset detector configure (3) . . . . . . . . . . . . . . . . . . . . . . . . . 33 Soft mute / others (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SoftStep I (5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SoftStep II / DC detector (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Loudness (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Volume / output gain (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Treble filter (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Middle filter (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Bass filter (11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Subwoofer / middle / bass (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Speaker attenuation (LF/RF/LR/RR) (13-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Subwoofer attenuation (subwoofer L/subwoofer R) (17-18) . . . . . . . . . . . . . . . . . . . . . . . . 40 Testing audio processor 1 (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Testing audio processor 2 (20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4/45
TDA7719
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Block circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 QD and FD configuration of QD4/FD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block diagram of mixing stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness attenuation @ fP = 400Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Loudness center frequencies @ Attn. = 15dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Loudness attenuation, fc=2.4kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Softmute timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass Control @ fC = 80Hz, Q = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass center frequencies @ gain = 14dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass quality factors @ gain = 14dB, fC = 80Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bass normal and DC mode @ Gain = 14dB, fc = 80Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle control @ fC = 1 kHz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Middle center frequencies @ gain = 14dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Middle quality factors @ gain = 14dB, fc = 1kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Treble Control @ fC = 17.5kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Treble center frequencies @ gain = 14dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Subwoofer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC offset detection circuit (simplified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TSSOP28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5/45
1
INPUT MULTIPLEXER
6/45
Block circuit diagram
Figure 1.
MUTE
QD1L
MAIN SELECTOR LOUDNESS VOLUME TREBLE MIDDLE BASS
SOFT MUTE MONO FADER
MIX
OUTLF
QD1G MONO FADER MIX OUTRF
QD1R
Block circuit diagram
QD2L
Block circuit diagram
QD2G
DIRECT PATH MONO FADER MIX OUTLR
QD2R
QD3L
QD3G
QD3R
REAR SELECTOR
MONO FADER
MIX
OUTRR
SUBWOOFER LPF
MONO FADER
MIX
OUTL2
FDL+ / QD4L FDL+ / QD4G FDR+ / QD4G FDR+ / QD4R
MIX SELECTOR MONO FADER MIX OUTR2
BEEP INPUT MUX OUT SUPPLY DIGITAL CONTROL I2C BUS DC-Offset Detector / Level Meter
VDD
CREF
GND
SCL SDA
WIN_IN / BEEP
WIN_TC / VREF
DC_ERR / LMOUT
TDA7719
TDA7719
Pin connections and pin descriptions
2
2.1
Pin connections and pin descriptions
Pin connections
Figure 2. Pin connections (top view)
2.2
Pin description
Table 2.
No. 1 2 3 4 5 6 7 8 9
Pin description
Pin name Description QD1 left input or SE1 left or MD3 positive input QD1 right input or SE1 right input or MD3 negative input QD1 common input or SE2 left input QD2 common input or SE2 right input QD2 left input or SE3 left input QD2 right input or SE3 right input QD3 left input QD3 common input QD3 right input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
QD1L / SE1L / MD3+ QD1R / SE1R / MD3QD1G / SE2L QD2G / SE2R QD2L / SE3L QD2R / SE3R QD3L QD3G QD3R
7/45
Pin connections and pin descriptions Table 2.
No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TDA7719
Pin description (continued)
Pin name Description QD4 left input or FD4L positive input or SE4 left input or MD1 positive input QD4 common input or FD4L negative input or SE4 right input or MD1 negative input QD4 common input or FD4R negative input or SE5 left input or MD2 negative input I/O I/O I/O I/O I/O O S
nd nd
QD4L / FD4+ / SE4L / MD1+ QD4G / FD4L- / SE4R / MD1QD4G / FD4R- / SE5L / MD2-
QD4R / FD4R+ / SE5R / QD4 right input or FD4R positive input or SE5 right input or MD2+ MD2 positive input CREF GND OUTR2 OUTL2 OUTRF OUTRR OUTLR OUTLF WinTC / VREF MUTE VDD SCL SDA DC_ERR / LMOUT WIN_IN / Beep Reference capacitor Ground Subwoofer output / 2 right output left output
O O O O O O O I/O S I I/O O I
Subwoofer output / 2 Front right output Rear right output Rear left output Front left output
DC offset detector filter or Vref output I2C bus data Supply I2C I
2C
bus clock bus data
DC offset detector output or Level meter output DC offset detector input or Beep input (Mono Single-Ended input)
8/45
TDA7719
Electrical specifications and characteristics
3
3.1
Electrical specifications and characteristics
Thermal data
Table 3.
Symbol Rth-j amb
Thermal data
Description Thermal resistance junction to ambient Value 114 Unit C/W
3.2
Absolute maximum ratings
Table 4.
Symbol VS Vin_max Tamb Tstg
Absolute maximum ratings
Parameter Operating supply voltage Maximum voltage for signal input pins Operating ambient temperature Storage temperature range Value 10.5 7 -40 to 85 -55 to 150 Unit V V C C
3.3
Table 5.
Symbol Supply Vs Is
Electrical characteristics
VS = 8.5V; Tamb= 25C; RL= 10k; all gains = 0dB; f = 1kHz; unless otherwise specified Electrical characteristics
Parameter Test condition Min. Typ. Max. Unit
Supply voltage Supply current
7.5 25
8.5 35
10 45
V mA
Input selector Rin VCL SIN Input resistance Clipping level Input separation All single ended inputs(1) Input Gain = 0dB 70 1.8 80 100 2 100 130 k VRMS dB
Differential stereo inputs Rin CMRR1 CMRR2 eNo Input resistance Common mode rejection ratio for main source Common mode rejection ratio for 2nd source Output noise @ speaker outputs Differential VCM=1 VRMS@ 1kHz VCM=1 VRMS@ 10kHz VCM=1 VRMS@ 1kHz 20Hz-20kHz, A-weighted; all stages 0dB 70 46 46 46 60 60 12 30 100 130 k dB dB dB V
9/45
Electrical specifications and characteristics Table 5.
Symbol Loudness control AMAX ASTEP fPeak(2) Max attenuation Step resolution fP1 Peak frequency fP2 fP3 Volume control GMAX AMAX ASTEP EA ET Max gain Max attenuation Step resolution Attenuation set error Tracking error DC steps Adjacent attenuation steps From 0dB to GMIN 0.1 0.5 13 -17 0.5 -0.75 15 -15 1 0 17 -13 1.5 +0.75 2 3 5 17 0.5 360 720 2200 15 1 400 800 2400 13 1.5 440 880 2600
TDA7719
Electrical characteristics (continued)
Parameter Test condition Min. Typ. Max. Unit
dB dB Hz Hz Hz
dB dB dB dB dB mV mV
VDC
Soft mute AMUTE
Mute attenuation T1 T2 T3 T4
80 0.16 0.32 3 10 2.7 32 3.1
100 0.48 0.96 8 16 0.80 1.6 13 20 0.6 45 3.3 58 3.5
dB ms ms ms ms V V k V
TD
Delay time
VTH Low VTH High RPU VPU Bass control
Low threshold for SM pin High threshold for SM pin Internal pull-up resistor Internal pull-up Voltage
fC1 Fc Center frequency fC2 fC3 fC4 Q1 QBASS(2) Quality factor Q2 Q3 Q4 CRANGE ASTEP DCGAIN Control range Step resolution Bass-DC-gain DC = off DC = on, Gain = 15dB
54 72 90 180 0.9 1.1 1.3 1.8 14 0.5 -1 3.5
60 80 100 200 1 1.25 1.5 2 15 1 0 4.4
66 88 110 220 1.1 1.4 1.7 2.2 16 1.5 +1 5.5
Hz Hz Hz Hz
dB dB dB dB
10/45
TDA7719 Table 5.
Symbol Middle control CRANGE ASTEP Control range Step resolution fC1 fc(2) Center frequency fC2 fC3 fC4 Q1 QBASS(2) Quality factor Q2 Q3 Q4 Treble control CRANGE ASTEP Clipping level Step resolution fC1 fc(2) Center frequency fC2 fC3 fC4 Speaker attenuators AMIN AMAX ASTEP AMUTE EE Min attenuation Max attenuation Step resolution Mute attenuation Attenuation set error DC steps
Electrical specifications and characteristics Electrical characteristics (continued)
Parameter Test condition Min. Typ. Max. Unit
14 0.5 400 0.8 1.2 2 0.45 0.65 0.9 1.1
15 1 500 1 1.5 2.5 0.5 0.75 1 1.25
16 1.5 600 1.2 1.8 3 0.55 0.85 1.1 1.4
dB dB Hz kHz kHz kHz
14 0.5 8 10 12 14
15 1 10 12.5 15 17.5
16 1.5 12 15 18 21
dB dB kHz kHz kHz kHz
-1 -89 0.5 80 Adjacent attenuation steps
0 -79 1 90
1 -69 1.5 2
dB dB dB dB dB mV
VDC
0.1
5
Audio outputs VCL ROUT RL CL VDC Clipping level Output impedance Output load resistance Output load capacitor DC voltage level 3.8 4.0 2 10 4.2 d = 0.3%; Byte8_D6=1 d = 1%; Byte8_D6=0 2 2.2 30 100 VRMS VRMS
k nF V
Subwoofer attenuator GMAX AMAX ASTEP AMUTE EE Max gain Max attenuation Step resolution Mute attenuation Attenuation set error 14 -89 0.5 80 15 -79 1 90 2 16 -69 1.5 dB dB dB dB dB
11/45
Electrical specifications and characteristics Table 5.
Symbol
TDA7719
Electrical characteristics (continued)
Parameter DC steps Test condition Adjacent attenuation steps Min. Typ. 0.1 Max. 5 Unit mV
VDC
Subwoofer lowpass fLP1 fLP(2) Lowpass corner frequency fLP2 fLP3 DC offset detection circuit V2 Vth Zero comp window size V3 V4 20 30 60 5 tsp Max rejected spike length 10 15 20 ICHDCErr IDISDCErr VOutH VOutH Level meter Vout VLEVEL TDEL General BW=20Hz to 20kHz AWeighted, all gain = 0dB BW=20Hz - 20kHz AWeighted, Output muted all gain = 0dB, A-weighted; Vo = 2VRMS VIN =1VRMS; all stages 0dB 80 12 6 104 0.01 90 0.2 30 25 V V dB % dB Output voltage range Output level Analog output delay time Vin = 1Vrms Vin = AC Grounded 0 1.2 -0.5 1.6 0 2 3.4 2.0 0.5 V V V s DCErr charge current DCErr discharge current DCErr high volotage DCErr low voltage 1 3.5 3 50 75 100 11 22 33 44 5 5 3.3 100 80 110 140 25 50 75 100 10 6.5 3.6 300 mV mV mV s s s s A mA V mV 72 108 144 80 120 160 88 132 176 Hz Hz Hz
eNO
Output noise
S/N D SC
Signal to noise ratio Distortion Channel separation left/right
1. When DC offset detector is not used, the impedance of mono single-ended input is 50k instead of 100k 2. Minimun, typical and maximum are calculate in according to simulation result. Functionality is guaranteed by measuring a directly correlated parameter.
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TDA7719
Description
4
4.1
Description
Input stages
The input stage (Main source and 2nd source) is configurable to adapt to different application. There are 7 different configurations which provide different input structure and different number of input sources as shown below.

4 x QD, 2 x QD + 3 x SE, 1 x QD + 5 x SE, 1 x QD + 3 x SE + 2 x MD, 3 x QD + 1 x FD, 3 x QD + 2 x SE, 1 x QD + 2 x SE + 1 x FD + 1 x MD, 1 x QD + 3 x SE + 1 x FD
Note:
QD = Quasi-Differential, SE = Single-ended input, FD = Full Differential, MD = mono Differential The configuration of the input stage is controlled by `Input Configuration' bits in I2C control table (Byte0 Bit5~Bit7). The table blow shows the configuration of input pins in different configurations.
Table 6.
Input pin configuration
Configuration bits (Byte0 Bit7~Bit5)
Pin
Pin name
"000" CFG0
"001" CFG1
SE1L IN0
"010" CFG2
SE1L IN0 SE1R SE2L
"011" CFG3
SE1L IN0 SE1R SE2L
"100" CFG4
QD1L QD1R QD1G IN0
"101" CFG5
QD1L QD1R QD1G QD2G IN0
"110" CFG6
MD3+ IN7 MD3SE2L IN4 SE2R
"111" CFG7
SE1L IN0 SE1R SE2L IN4 SE2R SE3L
1 2 3 4 5 6 7 8 9 10 11 12 13
QD1L_SE1L _MD3+ QD1R_SE1R _MD3QD1G_SE2L QD2G_SE2R QD2L_SE3L QD2R_SE3R QD3L QD3G QD3R QD4L_FD4+ _SE4L_MD1+ QD4G_FD4L _SE4R_MD1QD4G_FD4R_S E5L_MD2QD4R_FD4R+_ SE5R_MD2+
QD1L QD1R QD1G QD2G QD2L QD2R QD3L QD3G QD3R QD4L QD4G IN3 QD4G QD4R IN2 IN1 IN0
SE1R SE2L IN4 SE2R SE3L IN1 SE3R QD3L QD3G QD3R QD4L QD4G IN3 QD4G QD4R IN2
IN4 SE2R SE3L IN1 SE3R QD3L QD3G QD3R SE4L IN5 SE4R SE5L IN6 SE5R MD2+ MD1MD2IN2 SE3R QD3L SE2R SE3L
IN4 QD2G QD2L IN1 QD2R QD3L QD3G QD3R FD4L+ IN3 FD4LIN3 FD4RIN3 FD4R + SE5R SE5L IN6 FD4R+ FD4RSE4R IN2 QD2R QD3L QD3G QD3R SE4L IN5 FD4LIN2 SE3R QD3L QD3G QD3R FD4L+ IN1
QD2L
IN1
SE3L IN1
IN1 SE3R QD3L
QD3G IN2 QD3R MD1+
IN2
QD3G QD3R FD4L+ FD4L-
IN2
IN3
IN3 FD4RFD4R+
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Description
TDA7719 With different input configuration, the input source can be selected with input selector (Byte0/1 Bit0~Bit2). The following matrix defines the selector configuration of different input sources dependant on the configuration bits. Table 7. Selector configuration matrix
000 IN0 QD1 SE1 SE1 SE1 QD1 QD1 NA SE1 001 IN1 QD2 SE3 SE3 SE3 QD2 QD2 SE3 SE3 010 IN2 QD3 QD3 QD3 QD3 QD3 QD3 QD3 QD3 011 IN3 QD4 QD4 NA MD1/2 FD NA FD FD 100 IN4 NA SE2 SE2 SE2 NA NA SE2 SE2 101 IN5 NA NA SE4 NA NA SE4 NA NA 110 IN6 NA NA SE5 NA NA SE5 NA NA 111 IN7 NA NA NA NA NA NA MD3 NA
Selector Bits (Byte0/1 Bit2~Bit0) CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7
Note:
In each configuration, only the green cells are allowed. The red cells is not allowed. MD1/MD2 selection is defined by extra bit - `MD1/2 selection' in I2C control table (Bit3 of Byte0/1). The input stage can be configured to 0dB or 3dB gain with I2C bus. The 0dB configuration allows up to 2Vrms input signal level, while with 3dB gain, the internal signal will start to clip when input signal level is higher than 1.414Vrms. The Pin10~Pin13 can be configured as full differential input stage or quasi-differential input. When it is configured as quasi-differential input, both Pin11 and Pin12 are used as the QD common input pins. These two pins must be connected together externally in application. In this case the input impedance of QD4 common is reduced to 50k (half of QD4 left and right input). The diagram below shows both QD and FD configuration of QD4/FD4.
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TDA7719 Figure 3. QD and FD configuration of QD4/FD4
FULL DIFFERENTIAL QUASI DIFFERENTIAL
Description
FD4L+ 100k
1
QD4L 100k + OUTL
1
+ OUTL
FD4L100k
2
QD4G 100k
2
FD4R+ 100k
1
QD4G 100k + OUTR
1
+ OUTR
FD4R100k
2
QD4R 100k
2
4.2
Mixing
The device provides mixing function which allows the mixing source mixed into front and rear speaker output independently. The mixing source can be any single-ended input, mono-differential input or beep input (Mono single-ended input when DC offset detector is not used). In order to adjust the level of mixing signal, the mixing selector is followed with a 0dB~-31dB attenuator. The maximum mixing input signal level is 1.6Vrms for single-ended input and mono-differential input. For beep input, the maximum input signal level is about 1.4Vrms. The block diagram of the mixing function is shown below. Figure 4. Block diagram of mixing stage
SE Inputs MD Inputs Beep
Mixing Selector
0~-31dB
Speaker Attenuator
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Description
TDA7719 Since the input stage of this device has different configurations, the corresponding sources for mixing selector are also different according to the configurations. The following table defines the available sources for mixing under different configurations. Table 8. Available sources for mixing
000 MixIN0 NA SE1 SE1 SE1 NA NA MD3 SE1 001 MixIN1 NA SE2 SE2 SE2 NA NA SE2 SE2 010 MixIN2 NA SE3 SE3 SE3 NA NA SE3 SE3 011 MixIN3 NA NA SE4 MD1 NA SE4 NA NA 100 MixIN4 NA NA SE5 NA NA SE5 NA NA 101 MixIN5 NA NA NA MD2 NA NA NA NA 110 MixIN6 Beep Beep Beep Beep Beep Beep Beep Beep 111 MixIN7 Mute Mute Mute Mute Mute Mute Mute Mute
Mix selector bits (Byte2 Bit2~Bit0) CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7
Note:
Only green cells are allowed mixing input. The red cells are not allowed. The beep input is available only when DC offset detector function is not used.
4.3
Loudness
There are four parameters programmable in the loudness stage:
4.3.1
Loudness attenuation
Figure 5 shows the attenuation as a function of frequency at fP = 400Hz Figure 5. Loudness attenuation @ fP = 400Hz.
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TDA7719
Description
4.3.2
Peak frequency
Figure 6 shows the four possible peak-frequencies at 400, 800 and 2400Hz Figure 6. Loudness center frequencies @ Attn. = 15dB.
4.3.3
High frequency boost
Figure 7 shows the different Loudness shapes in low & high frequency boost. Figure 7. Loudness attenuation, fc=2.4kHz
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Description
TDA7719
4.3.4
Flat mode
In flat mode the loudness stage works as a 0dB to -15dB attenuator.
4.4
SoftMute
The digitally controlled SoftMute stage allows muting/demuting the signal with a I2C-bus programmable slope. The mute process can either be activated by the SoftMute pin or by the I2C-bus. This slope is realized in a special S-shaped curve to mute slow in the critical regions (see Figure 8). For timing purposes the Bit0 of the I2C-bus output register is set to 1 from the start of muting until the end of demuting. Figure 8. Softmute timing
EXT. MUTE
1
+SIGNAL
REF
-SIGNAL
1 I2C BUS OUT
D97AU634
Time
Note:
A started Mute action is always terminated and could not be interrupted by a change of the mute signal
4.5
SoftStep volume
When the volume-level is changed audible clicks could appear at the output. The root cause of those clicks could either be a DC Offset before the volume-stage or the sudden change of the envelope of the audio signal. With the SoftStep feature both kinds of clicks could be reduced to a minimum and are no more audible. The blend-time from one step to the next is programmable as 5ms or 10ms. The softstep control is described in detail in Chapter 4.10.
4.6
Bass
There are four parameters programmable in the bass stage:
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TDA7719
Description
4.6.1
Bass attenuation
Figure 9 shows the attenuation as a function of frequency at a center frequency of 80Hz. Figure 9. Bass Control @ fC = 80Hz, Q = 1
4.6.2
Bass center frequency
Figure 10 shows the four possible center frequencies 60, 80, 100 and 200Hz. Figure 10. Bass center frequencies @ gain = 14dB, Q = 1
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Description
TDA7719
4.6.3
Bass quality factors
Figure 11 shows the four possible quality factors 1, 1.25, 1.5 and 2. Figure 11. Bass quality factors @ gain = 14dB, fC = 80Hz
4.6.4
DC mode
In this mode the DC gain is increased by 4.4dB. In addition the programmed center frequency and quality factor is decreased by 25% which can be used to reach alternative center frequencies or quality factors. Figure 12. Bass normal and DC mode @ Gain = 14dB, fc = 80Hz
The center frequency, Q and DC-mode can be set fully independently.
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TDA7719
Description
4.7
Middle
There are three parameters programmable in the middle stage:
4.7.1
Middle attenuation
Figure 13 shows the attenuation as a function of frequency at a center frequency of 1kHz. Figure 13. Middle control @ fC = 1 kHz, Q = 1
4.7.2
Middle center frequency
Figure 14 shows the four possible center frequencies 500Hz, 1kHz, 1.5kHz and 2.5kHz. Figure 14. Middle center frequencies @ gain = 14dB, Q = 1
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Description
TDA7719
4.7.3
Middle quality factors
Figure 15 shows the four possible quality factors 0.5, 0.75, 1 and 1.25. Figure 15. Middle quality factors @ gain = 14dB, fc = 1kHz
4.8
Treble
There are two parameters programmable in the treble stage:
4.8.1
Treble attenuation
Figure 16 shows the attenuation as a function of frequency at a center frequency of 17.5kHz Figure 16. Treble Control @ fC = 17.5kHz.
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TDA7719
Description
4.8.2
Treble center frequency
Figure 17 shows the four possible center frequencies 10k, 12.5k, 15k and 17.5kHz. Figure 17. Treble center frequencies @ gain = 14dB
4.9
Subwoofer Filter
The subwoofer lowpass filter has Butterworth characteristics with programmable cut-off frequency (80 / 120 / 160Hz). The output phase can be selected between 0deg and 180deg. The input of subwoofer takes signal from bass filter output or output of input mux. Figure 18. Subwoofer control
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Description
TDA7719
4.10
Softstep control
In this device, the softstep function is available for volume, speaker, loudness, treble, middle and bass block. With softstep function, the audible noise of DC offset or the sudden change of signal can be avoided when adjusting gain setting of the block. For each block, the softstep function is controlled by softstep on/off control bit in the control table. The softstep transient time selection (5ms or 10ms) is common for all blocks and it is controlled by softstep time control bit. The softstep operation of all blocks has a common centralized control. In this case, a new softstep operation can not be started before the completion previous softstep. There are two different modes to activate the softstep operation. The softstep operation can be started right after I2C data sending, or the softstep can be activated in parallel after data sending of several different blocks. The two modes are controlled by the `act bit' (it is normally bit7 of the byte.) of each byte. When act bit is `0', which means action, the softstep is activated right after the date byte is sent. When the act bit is `1', which means wait, the block goes to wait for softstep status. In this case, the block will wait for some other block to activate the operation. The softstep operation of all blocks in wait status will be done together with the block which activate the softstep. With this mode, all specific blocks can do the softstep in parallel. This avoids waiting when the softstep is operated one by one.
Chip Addr
Sub Addr
0xxxxxxx | Softstep start here
Chip Addr
Sub Addr
1xxxxxxx
1xxxxxxx
......
0xxxxxxx | Softstep start here for all
1.
It is not allowed to cross 0dB with softstep directly. From plus gain to minus gain, it must go to +0dB first, then destination. From minus gain to plus gain, it must go to -0dB first, and then destination. When one block is in `wait for softstep' status, it is not allowed to send data to this block again before its softstep is completed. To know if there is a softstep in operation, it is possible to monitor the `busy' signal by I2C transmission mode (Section 5.1.2). When softstep is busy (busy=0), it is better to wait before sending new data until it is free (busy=1).
2. 3.
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TDA7719
Description
4.11
DC offset detector and level meter option
This device provide DC offset detector function and level meter function option. In one specific application, only one of the function can be used. The configuration of the function is controlled by I2C bus (Byte3 Bit7). When the device uses DC offset detector function, Pin22, Pin27 and Pin28 are used as WinTC, DCErr and WinIN for DC offset detector. When it is configured as level meter, DCErr becomes level meter output. In the mean time, WinIN is used as beep input (Mono singleended input for mixing), and WinTC becomes a reference voltage output (4V external DC voltage or 3.3V internal reference voltage).
Caution:
DC offset detector and level meter / Vref output / Beep / (mono single sided input) can not be used at the same time.
4.12
DC offset detector
Using the DC offset detection circuit (Figure 19) an offset voltage difference between the audio power amplifier and the APR's Front and Rear outputs can be detected, preventing serious damage to the loudspeakers. The circuit compares whether the signal crosses the zero level inside the audio power at the same time as in the speaker cell. The output of the zero-window-comparator of the power amplifier must be connected with the WinIn-input of the APR. The WinIn-input has an internal pull-up resistor connected to 5.5Volts. It is recommended to drive this pin with open-collector outputs only. To compensate for errors at low frequencies the WinTC-pin are implemented, with external capacitors introducing the same delay = 7.5k * Cext as the AC-coupling between the APR and the power amplifier introduces. For the zero window comparators, the time constant for spike rejection as well as the threshold are programmable. For electrical characteristics see Chapter 3 on page 9. A low-active DC-offset error signal appears at the DCErr output if the next conditions are both true: a) b) Front and rear outputs are inside zero crossing windows. The Input voltage VWinIn is logic low whenever at least one output of the power amplifier is outside the zero crossing windows.
After power-on, the external attached capacitor is rapidly charged (fast-charge) to overcome a false indication.
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Description Figure 19. DC offset detection circuit (simplified)
TDA7719
4.13
Level meter
In case of not using DC offset detector, the three pins used for this function can be configured as other functions. Pin27 (DC_Err / LMOUT) then becomes the level meter output. The level meter block takes signal after main input selector and mix signal into mono, then rectify the signal and detect the peak of the signal. The output stage of level meter removes the DC voltage of the signal and the output voltage level shows exactly the Vpeak of signal. Since the discharge time constant of the level meter is quite slow, it is necessary to reset level meter regularly (with I2C bus control Byte3 Bit6) to get correct peak information of the signal.
4.14
Output gain control
The output stage of the device can provide a option to have additional 1dB gain in order to boost the maximum output level to 2.2Vrms with maximum 1% distortion.
4.15
Audioprocessor testing
In the test mode, which can be activated by setting bit D7 of the I2C subaddress byte and bit D0 of the testing-audioprocessor byte, several internal signals are available at the QD1L pin. In this mode, the input resistance of 100kOhm is disconnected from the pin. Internal signals available for testing are listed in the data-byte specification.
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TDA7719
Description
4.16
Test circuit (3 x QD + 1 x FD + DC offset detector)
Figure 20. Test circuit
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I2C Bus specification
TDA7719
5
5.1
I2C Bus specification
Interface protocol
The interface protocol comprises:

a start condition (S) a chip address byte (the LSB determines read/write transmission) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P) the max. clock speed is 500kbits/s 3.3V logic compatible
5.1.1
S 10
Receive mode
0010 0 R/W ACK TS X AI A4 A3 A2 A1 A0 ACK DATA ACK P
S = Start R/W = "0" -> Receive Mode (Chip can be programmed by P) "1" -> Transmission Mode (Data could be received by P) ACK = Acknowledge P = Stop
TS = Testing mode AI = Auto increment
5.1.2
S 1 0
Transmission mode
0 0 1 0 0 R/W ACK X X X X X X BZ SM ACK P
SM = Soft mute activated for main channel BZ = Softstep Busy (`0' = Busy) X = Not Used The transmitted data is automatic updated after each ACK. Transmission can be repeated without new chip address.
5.1.3
Reset condition
A Power-On-Reset is invoked if the supply voltage is below than 3.5V. After that the registers are initialized to the default data written in following tables.
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TDA7719 Table 9.
MSB I2 I1 I0 A4 A3 A2 A1
I2C Bus specification Subaddress (receive mode)
LSB Function A0 Testing Mode Off On
0 1 x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Not Used Auto Increment Mode Off On Input Configuration / Main Source Selector 2nd Source Selector / Direct Path Mixing Source / Mixing Gain Mix Control / Level Meter / DC Offset Detector Config Soft Mute / Others Soft Step I Soft Step II / DC-detector Loudness Volume / Output Gain Treble Middle Bass Subwoofer / Middle / Bass Speaker Attenuator Left Front Speaker Attenuator Right Front Speaker Attenuator Left Rear Speaker Attenuator Right Rear Subwoofer Attenuator Left Subwoofer Attenuator Right Testing Audio Processor 1 Testing Audio Processor 2
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I2C Bus specification
TDA7719
5.2
Table 10.
MSB D7
Data byte specification
The default power on status of the registers is written with underline. Input configuration / main selector (0)
LSB Function D6 D5 D4 D3 D2 D1 D0 Main source selector IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 MD1/2 configuration for main selector MD1 MD2 Main source input gain select 0dB 3dB Input configuration CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7
0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Note:
For detailed input source and input stage configuration, please refer to Section 4.1.
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TDA7719 Table 11.
MSB D7 D6 D5 D4 D3 D2 D1
I2C Bus specification 2nd Source selector / direct path (1)
LSB Function D0 2nd Source Selector IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 MD1/2 Configuration for 2nd Selector MD1 MD2 2nd Source Input Gain Select 0dB 3dB QD2 Bypass (Front) on Off QD3 Bypass (Rear) on Off QD4 Bypass (Subwoofer) on Off
0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Note:
For detailed input source and input stage configuration, please refer to Section 4.1. To active QD3 Bypass (Rear) function, it needs to set Byte3_D4 to "Direct Path / 2nd Source" also.
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I2C Bus specification Table 12.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7719
Mixing source / mixing gain (2)
LSB Function D0 Mixing Source Selector IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 Mixing Attenuator 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB -28dB -29dB -30dB -31dB
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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TDA7719 Table 13.
MSB D7 D6 D5 D4 D3 D2 D1
I2C Bus specification Mix control / level meter / dc offset detector configure (3)
LSB Function D0 Mix To Front Left On Off Mix To Front Right On Off Mix To Rear Left On Off Mix To Rear Right On Off Rear Speaker Input Configuration Direct Path / 2nd Source Main Signal Reference Output Select Internal Vref (3.3V) External Vref (4V) Level Meter Reset Normal Reset DC Offset Detector / Level Meter Config Level Meter DC Offset Detector
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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I2C Bus specification Table 14.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7719
Soft mute / others (4)
LSB Function D0 Soft Mute On Off Pin Influence for Mute Pin and IIC IIC Soft Mute Time 0.48ms 0.96ms 7.68ms 15.36ms Subwoofer Input Configuration Input Mux Bass Output Subwoofer Enable (OUTL3 & OUTR3) On Off Fast Charge On Off Anti-Alias Filter On Off (bypass)
0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1
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TDA7719 Table 15.
MSB D7 D6 D5 D4 D3 D2 D1
I2C Bus specification SoftStep I (5)
LSB Function D0 Loudness Soft Step On Off Volume Soft Step On Off Treble Soft Step On Off Middle Soft Step On Off Bass Soft Step On Off Speaker LF Soft Step On Off Speaker RF Soft Step On Off Speaker LR Soft Step On Off
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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I2C Bus specification Table 16.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7719
SoftStep II / DC detector (6)
LSB Function D0 Speaker RR Soft Step on off Subwoofer Left Soft Step on off Subwoofer Right Soft Step on off Soft Step Time 5ms 10ms Zero-comparator Window size 100mV 75mV 50mV Spike rejection time constant 11s 22 s 33 s 44 s
0 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 1 0 1 0 1 0
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TDA7719 Table 17.
MSB D7 D6 D5 D4 D3 D2 D1
I2C Bus specification Loudness (7)
LSB Function D0 Attenuation 0dB -1dB : -14dB -15dB Center Frequency Flat 400Hz 800Hz 2400Hz High Boost on off Soft Step Action act wait
0 0 : 1 1 0 0 1 1 0 1 0 1 0 1 0 1
0 0 : 1 1
0 0 : 1 1
0 1 : 0 1
Table 18.
MSB D7
Volume / output gain (8)
LSB Function D6 D5 D4 D3 D2 D1 D0 Gain/Attenuation -15dB -14dB : -1dB 0dB 0dB +1dB : +14dB +15dB Not used Output Gain 1dB 0dB Soft Step Action act wait
0 0 : 0 0 1 1 : 1 1 x 0 1 0 1
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 1 : 0 1 1 0 : 1 0
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I2C Bus specification Table 19.
MSB D7 D6 D5 D4 0 0 : 0 0 1 1 : 1 1 0 0 1 1 0 1 0 1 0 1 D3 0 0 : 1 1 1 1 : 0 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0
TDA7719
Treble filter (9)
LSB Function D0 0 1 : 0 1 1 0 : 1 0 Gain/Attenuation -15dB -14dB : -1dB 0dB 0dB +1dB : +14dB +15dB Treble Center Frequency 10.0kHz 12.5kHz 15.0kHz 17.5kHz Soft Step Action act wait
Table 20.
MSB D7
Middle filter (10)
LSB Function D6 D5 D4 D3 D2 D1 D0 Gain/Attenuation -15dB -14dB : -1dB 0dB 0dB +1dB : +14dB +15dB Middle Q Factor 0.5 0.75 1 1.25 Soft Step Action act wait
0 0 : 0 0 1 1 : 1 1 0 0 1 1 0 1 0 1 0 1
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 0 : 1 1 1 1 : 0 0
0 1 : 0 1 1 0 : 1 0
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TDA7719 Table 21.
MSB D7 D6 D5 D4 0 0 : 0 0 1 1 : 1 1 0 0 1 1 0 1 0 1 0 1 D3 0 0 : 1 1 1 1 : 0 0 D2 0 0 : 1 1 1 1 : 0 0 D1 0 0 : 1 1 1 1 : 0 0
I2C Bus specification Bass filter (11)
LSB Function D0 0 1 : 0 1 1 0 : 1 0 Gain/Attenuation -15dB -14dB : -1dB 0dB 0dB +1dB : +14dB +15dB Bass Q Factor 1.0 1.25 1.5 2.0 Soft Step Action act wait
Table 22.
MSB D7
Subwoofer / middle / bass (12)
LSB Function D6 D5 D4 D3 D2 D1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D0 0 1 0 1 Subwoofer Cut-off Frequency flat 80Hz 120Hz 160Hz Subwoofer Output Phase 180 deg 0 deg Middle Center Frequency 500Hz 1000Hz 1500Hz 2500Hz Bass Center Frequency 60Hz 80Hz 100Hz 200Hz Bass DC Mode on off
0 1
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I2C Bus specification Table 23.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7719
Speaker attenuation (LF/RF/LR/RR) (13-16)
LSB Function D0 Gain/Attenuation 0dB 0dB : 0dB 0dB -1dB : -78dB -79dB mute Soft Step Action act wait
0 0 : 0 0 0 : 1 1 1 0 1
0 0 : 0 0 0 : 0 0 1
0 0 : 0 1 1 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 1 : 1 0 1 : 0 1 x
Table 24.
MSB D7
Subwoofer attenuation (subwoofer L/subwoofer R) (17-18)
LSB Function D6 D5 D4 D3 D2 D1 D0 Gain/Attenuation +0dB +1dB : +15dB -0dB -1dB : -78dB -79dB mute Soft Step Action act wait
0 0 : 0 0 0 : 1 1 1 0 1
0 0 : 0 0 0 : 0 0 1
0 0 : 0 1 1 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 0 : 1 0 0 : 1 1 x
0 1 : 1 0 1 : 0 1 x
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TDA7719 Table 25.
MSB D7 D6 D5 D4 D3 D2 D1
I2C Bus specification Testing audio processor 1 (19)
LSB Function D0 Audio Processor Testing Mode off on Test Multiplexer at QD1L (1) DCDet Vth High DCDet Vth Low VolumeoutL IntZeroErr InGainL LoudoutL BassoutL MidoutL Ref5V5 VGB1.26 SMCLK TrebleoutL SSCLK Clock200k REQ SDCLK Clock Fast Mode (2) on Off Clock Source (2) external (at mute pin) Internal (200kHz) Not Used
0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 x
1. The control bit needs both I2C test mode on & sub-address test mode on. 2. The control bit does not depend on test mode.
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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I2C Bus specification Table 26.
MSB D7 D6 D5 D4 D3 D2 D1
TDA7719
Testing audio processor 2 (20)
LSB Function D0 Test Architecture (1) normal Split Oscillator Clock (2) 400kHz 800kHz Softstep Curve (2) S-Curve Linear Curve Manual Set Busy Signal (1) Auto Auto 0 1 Request for Clk Generator (1) Allow Allow Stopped Stopped Not Used
0 1 0 1 0 1 0 0 1 1 0 0 1 1 x x x 0 1 0 1 0 1 0 1
1. The control bit needs sub-address test mode on 2. The control bit does not depend on test mode.
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TDA7719
Package information
6
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. TSSOP28 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 b c D
1
inch MAX. 1.200 MIN. TYP. MAX. 0.047 0.002 0.031 0.007 0.004 0.378 0.244 0.170 0.382 0.252 0.173 0.026 0.750 0.018 0.024 0.039 0.030 0.039 0.006 0.041 0.012 0.008 0.386 0.260 0.177
TYP.
OUTLINE AND MECHANICAL DATA
0.050 0.800 0.190 0.090 9.600 6.200 4.300 9.700 6.400 4.400 0.650 0.450 0.600 1.000 1.000
0.150 1.050 0.300 0.200 9.800 6.600 4.500
E E11 e L L1 k aaa
0 (min.), 8 (max.) 0.100 0.004
TSSOP28
Thin Shrink Small Outline Package
JEDEC MO-153-AC
Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side.
0128292 B
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Revision history
TDA7719
7
Revision history
Table 27.
Date 16-Jul-2007 7-Jan-2007
Document revision history
Revision 1 2 Initial release. Added and updated the values on the Table 5: Electrical characteristics. Document status promoted from preliminary data to datasheet. Changes
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TDA7719
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